Magnetic random access memory (MRAM) for non-volatile storage of data is typically implemented with a magneto-tunneling junction (MTJ) whose two resistance states (“high” and “low”) encode the binary bits “1” and “0”. The MTJ has a hard and a soft magnetic layer separated by a spacer. Each of the two layers is usually elliptical and has two stable magnetization states along the major axis of the ellipse. When the magnetizations of the two layers are parallel, the MTJ resistance is low, and when they are anti-parallel, the resistance is high. Writing a bit into an MRAM cell therefore merely involves changing the resistance of the MTJ by orienting the magnetization of the soft layer either parallel or anti-parallel to that of the hard layer.
The oldest bit writing scheme used a current-induced magnetic field to orient the soft layer's magnetization. More recent schemes use spin transfer torque (STT) generated by passing a current through the MTJ, or domain wall motion, or manipulation of Rashba spin-orbit interaction at interfaces, or modulation of interface exchange coupling at a ferroelectric/ferromagnetic interface with an electric field, to orient the soft layer's magnetization. Most of these schemes are extremely dissipative and result in dissipating ˜107 kT of energy per bit at room temperature (1 kT=4×10−21 Joules at room temperature), making them extremely energy-inefficient and power hungry. Recently, more energy-efficient schemes have been demonstrated and involve rotating the soft layer's magnetization either with a spin-polarized current generated via spin-Hall effect, or with voltage-controlled magnetic anisotropy in oxides, or with voltage controlled spin-orbit torque in ferromagnets and magnetically doped topological insulators, or with voltage-generated uniaxial strain/stress in a shape anisotropic magnetostrictive-piezoelectric (multiferroic) nanomagnet. The strain/stress is generated by applying an electrical voltage across the piezoelectric layer of the multiferroic nanomagnet.
Unfortunately, strain/stress as used in methods in the preceding paragraph can only rotate the magnetization of an elliptical multiferroic nanomagnet by up to ˜90°, which means that it is not able to “flip” the magnetization from one stable state to the other since that requires a ˜180° rotation. When the magnetization is rotated to ˜90°, there is an approximately equal probability of the magnetization going to either of the two stable orientations once strain is removed. This gives a ˜50% probability of successfully writing a bit into an MRAM cell. The only way to reliably achieve a full 180° rotation with each application of stress is to withdraw the stress as soon as the magnetization vector has rotated exactly 90° from the original orientation. If this withdrawal is timed with very high precision, a residual torque due to the magnetization vector's out of plane component may continue to rotate it beyond 90° and achieve a “flip” with very high probability (>99.99% at room temperature), resulting in very high likelihood of writing a bit successfully into an MRAM cell. The problem with this methodology, however, is that such precisely timed withdrawal of stress requires a feedback mechanism that determines when the magnetization has completed the 90° rotation and feeds that information back to the voltage generator to withdraw the stress at exactly the right juncture. Such feedback circuitry introduces extremely high dissipative energy loss and defeats the benefits of using straintronic memory. This makes this strategy unappealing.
With respect to Boolean logic, there is significant interest in ‘non-volatile logic’ because the ability to store and process information with the same device affords immense flexibility in designing computing architectures. Non-volatile logic based architectures can reduce overall energy dissipation by eliminating refresh clock cycles, improve system reliability, improve reliability by eliminating processor-memory communication, and produce ‘instant-on’ computers with virtually no boot delay. A number of non-volatile universal logic gates have been proposed to date, but they do not necessarily satisfy all the requirements for a logic gate and therefore may not be usable in all circumstances. Cowburn et al. (Cowburn, R. P. & Welland, M. E. Room temperature magnetic quantum cellular automata. Science 287, 1466-1468 (2000)) proposed an idea where digital bits are stored in the magnetization orientations of an array of dipole-coupled nanomagnets, and dipole coupling between neighbors elicits logic operation on the bits. This gate is not concatenable since the input and output bits are encoded in dissimilar physical quantities: the inputs are encoded in directions of magnetic fields and the output is encoded in the magnetization orientation of a magnet. Thus, the output of a preceding gate cannot act as the input to the succeeding gate without additional transducer hardware to convert the magnetization orientation of a nanomagnet into the direction of a magnetic field. Such transducer hardware drastically reduces the energy efficiency of the logic gates and makes them more error-prone. The gate also lacks true power gain since the energy needed to switch the output comes from the inputs and not an independent source such as a power supply. This makes its operation unreliable. More importantly, logic information cannot unidirectionally stream from the input gates to the output gates without multiphase clocking of the gates [a scheme known as “Bennett clocking”; C. H. Bennett, The thermodynamics of computation—A review. International Journal of Theoretical Physics, 21, 905-940 (1982)] which dissipates exorbitant amount of energy. Bennett clocking cannot be dispensed with since the unidirectional streaming is required for every logic operation. Additionally, the strength of dipole coupling between magnets, which is critical for logic operation, decreases as the square of the magnet's volume. This limits scalability because the magnets' sizes cannot be scaled down arbitrarily without endangering safe operation of the gates. Finally, dipole coupling between the magnets is never sufficiently resilient against thermal noise, resulting in unacceptably large dynamic bit error probability in dipole-coupled logic gates.
Ney et al. (Ney, A., Pampuch, C., Koch, R. & Ploog, K. H. Programmable computing with a single magnetoresistive element. Nature 425, 485-487 (2003)) proposed a different construct where a NAND gate was implemented with a single magneto-tunneling junction (MTJ) placed close to four current lines, two of which ferry the two input bits to the gate, the third is required for an initialization operation, and the fourth carries the output. The magnetic fields generated by the input currents flip the magnetization of the MTJ's soft layer and switch its resistance, thereby switching the magnitude of the output current and performing NAND logic operation. This gate has the advantage of not requiring Bennett clocking and has also been experimentally demonstrated (Wang, J., Meng, H & Wang, J-P, Programmable spintronics logic device based on magnetic tunneling junction element. J. Appl. Phys., 97, 10D509 (2005)). Unfortunately, this gate too is not directly concatenable since the input bits are encoded in the directions of the input currents while the output bit is encoded in the magnitude of the output current. Moreover, since it is difficult to confine magnetic fields to small regions, the separation between neighboring devices must be large. Individual devices can be small in size, but because the inter-device pitch is large, the device density will be small. Finally, there is some chance that the output current can also, by itself, switch the magnetization of the magnetic layers and therefore affect its own state. This is equivalent to lack of isolation between the input and the output. Thus, while these devices are interesting in their own right, they may not be universally usable.
A more recent scheme that overcomes some of the above shortcomings was proposed by Behin-Aein et al. (Behin-Aein, B., Datta, D., Salahuddin, S. & Datta S., Proposal for an all-spin logic device with built-in memory. Nature Nanotech. 5, 266-269 (2010)) and Srinivasan et al. (Srinivasan, S., Sarkar, A., Behin-Aein, B. & Datta, S. All-spin logic device with in-built non-reciprocity. IEEE Trans. Magn. 47 4026-4032 (2011)). It implements a non-volatile universal logic gate with magnets switched by spin currents as opposed to charge currents (hence the name “all-spin-logic”, abbreviated as ASL). Unlike charge currents, spin currents ideally dissipate no energy and therefore it was thought that this paradigm will be extremely energy-efficient. However, spin currents ultimately do require flow of charge currents (whether the spin current is generated by a spin polarizer or the “spin-Hall effect”) and hence some dissipation is unavoidable. More importantly, providing isolation between input and output requires introducing an asymmetry in the gate. The original ASL idea (Behin-Aein, B., Datta, D., Salahuddin, S. & Datta S., Proposal for an all-spin logic device with built-in memory. Nature Nanotech. 5, 266-269 (2010)) proposed introducing this ‘asymmetry’ via different spin-injection efficiencies (engineered with tunnel barriers) at the input and output ends, while a later idea suggested introducing a ground terminal asymmetrically disposed between the input and output magnets (Srinivasan, S., Sarkar, A., Behin-Aein, B. & Datta, S. All-spin logic device with in-built non-reciprocity. IEEE Trans. Magn. 47 4026-4032 (2011)). The latter idea (simpler of the two) invariably necessitates charge current flow with accompanying dissipation. Recent calculations (Nikonov D. E. & Young, I. A., Overview of beyond-CMOS devices and a uniform methodology for their benchmarking. Proc. IEEE, 101, 2498 (2013) and Sharad, M., Yogendra, K., Gaud, A., Kwon, K-W & Roy, K. Ultrahigh density, high performance and energy-efficient all-spin logic. arXiv:1308.2280) have predicted that ASL is not particularly energy-efficient; the energy-delay product exceeds 10−25 Joules-sec which makes it two orders of magnitude worse than traditional CMOS gates. That is a high price to pay for non-volatility.
Moreover, both computation and communication between gates are carried out with a sequence of clock pulses. Unfortunately, its error-resilience has not been examined. Normally, magnetic devices are much more error-prone than transistors since magnetization dynamics is easily disrupted by thermal noise. Logic has stringent requirements on error rates, and it is important to evaluate the dynamic bit error probability of any gate to assess its viability.
Finally, the most important metric for a logic gate is the energy-delay cost. All existing non-volatile magnetic logic schemes fail in this area. The scheme in Ney et al. uses current generated magnetic fields to switch magnets and hence would dissipate at least 109 kT of energy per gate operation at room temperature to switch in ˜1 ns (energy-delay product=4×10−2 J-s). A different experiment conducted to demonstrate this scheme used on-chip current-generated magnetic fields to switch magnets and ended up dissipating approximately 1012 kT of energy per switching event, despite switching in ˜1 μs (energy-delay product=4×10−15 J-s). The scheme in Behin-Aein et al. is expected to dissipate between 105 and 106 kT of energy when it switches in 1 ns (energy-delay product=4×1025−4×1024 J-s). In contrast, a low-power transistor may dissipate only 103 kT of energy when it switches in 0.1 ns (energy-delay product=3×1028 J-s). In short, all the above non-volatile schemes appear to be far inferior to transistors in energy-delay product, which may preclude their widespread application, despite the non-volatility.